In an integrated semiconductor memory such as a DRAM (Dynamic Random Access Memory) semiconductor memory, the memory cells are arranged in a matrix-type memory cell array. The matrix-type configuration of the memory cell array results from the essentially vertical word lines and horizontal bit lines. An individual DRAM memory cell comprises a selection transistor, where the controllable path is connected to the first electrode of a storage capacitor. The second electrode of the storage capacitor is connected to a reference potential. A control terminal of the selection transistor is connected to one of the word lines. The controllable path of the selection transistor is connected to one of the bit lines. Thus, each crossover point between a word line and a bit line represents the location of a memory cell. In order to read out cell information stored in the memory cell, the selection transistor is switched into the on state by applying a corresponding voltage potential to the word line. The charge stored on the storage capacitor flows via the controllable path of the selection transistor to the bit line and alters the potential thereof. In order to assess the cell information, sense amplifiers are employed, designed as differential amplifiers. The sense amplifiers are connected to the end of the bit line. Area optimization of the sense amplifiers presupposes that half of the data applied to the chip, the so-called logical data, are stored within the memory cell with inverse polarity. In other words, the logical data applied to a data input terminal of the integrated semiconductor memory with a high voltage level, e.g., the logic state one, are stored in the storage capacitor of the associated memory cell with a low electrical charge level, e.g., logic state zero. Equivalently, logical data which are applied to the data input terminal with a low voltage level, e.g., logic state zero, will be stored in the storage capacitor of a memory cell with a high electrical charge, e.g., logic state one. The electrical charge stored in the memory cell represents the physical cell information. In the case of approximately half of the memory cells, the physical cell information items, the so-called physical data, do not correspond to the logical data applied to the data input terminal. Such memory cells are referred to as complement cells. Alternately, the other half of the memory cells or true cells, the physical data corresponds to the logical data applied to the data input terminal.
FIG. 1 shows a detail from a memory cell array. The vertically running lines form the word lines and the horizontally running lines represent the bit lines. A memory cell is arranged at the crossover point between a word and bit line. The memory cells designated by SZ1 represent true cells, whereas the memory cells designated by SZ2 are designed as complement cells.
For the purpose of area optimization, the sense amplifiers are arranged in a first strip SF1 and a second strip SF2. The first sense amplifiers SAbc1, SAbc2 located in the first strip SF1 are connected to a first secondary sense amplifier SSA1. The second sense amplifiers SAa1 and SAa2 and respectively SAd1 and SAd2 located in the second strip SF2 are connected to a second secondary sense amplifier SSA2. Between the first and second sense amplifier strips, the bit lines BL are arranged in the form of a bit line twist. FIG. 1 illustrates a first bit line twist between the second sense amplifiers SAa and the first sense amplifiers SAbc and a second bit line twist between the first sense amplifiers SAbc and the second sense amplifiers SAd. Within the first bit line twist and the second bit line twist, the first and second word lines WL1 and WL2 run in a word line strip SFb and SFd, respectively, and a word line strip SFa and SFc, respectively. In the case of the bit line twist illustrated, the bit lines do not run parallel between the first and second sense amplifiers, but rather are offset with respect to one another in sections. The arrangement of the bit lines in the form of a bit line twist reduces interfering coupling influences between the individual bit lines.
The memory cells situated at each crossover point between a word and bit line can be addressed by a plurality of address bits. In the case of the example shown in FIG. 1, the address bits X0, . . . , X10 are used for addressing a memory cell Z, of which address bits, the address bits X0, X1, X9 and X10 are illustrated for the sake of better clarity. In FIG. 1, it is possible to select for example memory cells, via the address bits X0 and X1, which can be driven by the word lines N0, N1, N2 and N3 within the word line strips SFb and SFd and respectively memory cells which can be driven via the word lines R0, R1, R2 and R3 within the word line strips SFa and SFc. The address bits X9 and X10 select one of the four word lines strips SFa, SFb, SFc and SFd. In this case, the word lines designated by R in the word line strip SFa and SFc drive redundant memory cells, whereas the word lines designated by N in the word line strip SFb and SFd drive regular memory cells. If a regular memory cell has been identified as defective during the production process, then the defective memory cell is generally replaced by a redundant memory cell. The repair of defective memory cells is limited by the number of redundant memory cells present, which make up approximately 1% to 2% of all the memory cells of a memory cell array. With continued reference to FIG. 1, the process replacing defective memory cells with redundant memory cells is detailed below.
If, for example, a short circuit between two word lines has arisen during the production process, then all the memory cells which are driven by these two word lines can be replaced by redundant memory cells situated on defect-free word lines. In order to be able to efficiently repair short circuits between word lines, the word lines for driving the redundant memory cells are typically arranged in quadruples. If, for example, a short circuit occurs between the regular word line N3 and N2 in the word line strip SFd, then the memory cells which are driven via the word lines N0, . . . , N3 in the word line strip SFd are replaced by redundant memory cells which are driven via the redundant word lines R0, . . . , R3 in the word line strip SFc. Thus, regular defective memory cells of the word line strip SFd of the second bit line twist are replaced by redundant memory cells in the word line strip SFc. If memory cells of one word line strip are replaced by redundant memory cells of another word line strip within the same bit line twist, a so-called topologically incorrect word line repair results. In the case of the topologically incorrect word line repair, the assignment of the address bits X0 and X1 identifying the word line of repaired memory cells of a defective word line to redundant memory cells of a redundant word line is preserved. By way of example, the two memory cells Z3 are driven by the sense amplifier SAd1 and which are driven via the short-circuited regular word lines N1 and N2. The two memory cells of Z3 are replaced by the two redundant memory cells Z3′ which are driven via the defect-free redundant word lines R1 and R2. As can be seen from FIG. 1, the defective true memory cells Z3 are replaced by the redundant complement memory cells Z3′. Equivalently, the two memory cells Z4 which are driven by the sense amplifier SAd1 and which are driven via the word lines N0 and N3 are replaced by the two redundant memory cells Z4′ which are driven via the redundant word line R0 and R3. The defective complement memory cells Z4 are thus replaced by the redundant true memory cells Z4′.
The replacement of defective memory cells by redundant memory cells or the replacement of defective word line quadruples by redundant word line quadruples is generally effected during the production process of an integrated semiconductor memory at the wafer level, in the so-called front end of a production line. At the end of the production process, the finished integrated semiconductor memory chips are once again finally tested for functionality in the so-called back end of a production line.
The procedure, for example of a so-called retention test, will now be explained with reference to FIG. 2. A retention test involves testing whether the memory cells retain cell information in the form of a charge stored on the storage capacitor of the memory cell over a relatively long period of time, or whether the storage capacitor is discharged for example via a leakage path. At the beginning of such a retention test, an information item is read into the memory cell to be tested. After a specific retention time T, the information item is read out again from the memory cell in order to test whether the charge has been maintained on the storage capacitor.
FIGS. 2A-2F show a data input and data output terminal DIO for reading data in and out and an amplifier V connected to a memory cell of the memory cell type SZ1 or SZ2. The memory cell is illustrated in a greatly simplified manner, and contains a storage capacitor SC, the first electrode of which is connected to the amplifier V, and at the same time, to a ground reference terminal M, via a leakage path L. The second electrode is connected to the ground reference terminal M. The memory cells of the memory cell type SZ1 are true cells, whereas the memory cells of the memory cell type SZ2 represent complement cells.
FIGS. 2A and 2B show two defective true memory cells with a leakage path L. At the beginning of the retention test, a 1 information item, that is to say a high charge level, is applied to the data input terminal DIO and stored on the storage capacitor SC via the amplifier V. FIG. 2B shows the state of the defective true memory cell after the retention time T has elapsed. The storage capacitor has been completely discharged to ground via the leakage path. A 0 information item arises at the data output terminal DIO. The memory cell of the memory cell type SZ2 can be unambiguously detected as defective by this test.
FIGS. 2C and 2D show a defective complement memory cell with a leakage path L. At the beginning of the retention test, a 1 information item, that is to say a high charge level, is applied to the data input terminal DIO and stored on the storage capacitor SC in inverted fashion, in other words with a low charge level, via the amplifier V and a bidirectional inverter INV. FIG. 2D shows the state of the defective complement memory cell after the retention time T has elapsed. The storage capacitor has been completely discharged to ground via the leakage path L. The leakage path L remains undiscovered during this test for a complement memory cell since the bidirectional inverter inverts the low charge level of the storage capacitor again, so that the 1 information item that was stored in the defective complement memory cell at the beginning of the retention test appears again at the data output terminal DIO after the retention time T has elapsed.
FIGS. 2E and 2F show a successful retention test for testing the same complement memory cell. At the beginning of the retention test, a 0 information item, e.g., a low charge level, is applied to the data input terminal DIO and stored in inverted fashion, that is to say with a high charge level, via the amplifier V and the bidirectional inverter INV. FIG. 2F shows the state of the defective complement memory cell after the retention time T has elapsed. The storage capacitor, which was charged with a high charge level via the inverter at the beginning of the retention test, has been completely discharged to ground after the retention time T has elapsed. At the data output terminal DIO, the bidirectional inverter and the amplifier V generate a 1 information item corresponding to a high charge level. A 1 information item thus occurs at the data output terminal at the end of the retention test, whereas a 0 information item was stored at the beginning of the retention test. The defective complement memory cell can be unambiguously detected as defective by means of this test.
Complement memory cells, during a retention test, can be tested with a 0 information item at the data input and data output terminal, while true memory cells can be tested with a 1 information item at the data input and data output terminal. If a defective true memory cell has been replaced by a redundant complement memory cell in the front end during a topologically incorrect word line repair, then test data for testing this repaired memory cell should be applied to the data input and data output terminal in inverted fashion in the back end of the production line. Otherwise, defective memory cells remain undiscovered.
During relatively long retention tests, the memory cells have been written to with one data topology, for example a 1 or 0 information item, in order to save test time. On the basis of the evaluation of such functional tests, it is known that there is a potential risk of undiscovered defective memory cells on at least 2000 memory cells per topologically incorrect word line repair for approximately 1% of the repairable semiconductor memory chips. This risk is currently accepted for particularly long functional tests, such as special retention tests, for example. For shorter tests, attempts are made to close this test gap by repeating the test with inverted data. However, this generally results in the test time being doubled.